CST MICROWAVE STUDIO® (CST MWS) was the only commercial software to solve a complex IC package benchmark set by IBM. This benchmark was set in the scope of the 15th Conference on Electrical Performance of Electronic Packaging (EPEP 2006, www.epep.org) during a special session hosted by IBM on the "Parallelization of EM Full-Wave Solvers for Product-Level Problems".
The benchmark was a complete IC package, provided as a Cadence® Allegro® layout with 8 metallization layers and a total of 40,000 geometrical entities. Various views of the structure are presented in Fig. 1. The problem involved a group of 20 fan-out lines and the associated differential pair clock lines. S-parameters were sought for at least four lines.
Using the EDA Link provided in CST MWS, the layout data of the PCB can be easily transformed into a 3D model. The link supports various industry standards, like Zuken 5000®, ODB++®, and Mentor Graphics® ASCII files. During the import stage it is already possible to define geometry and material parameters and also the positions of the excitation ports. Furthermore, parts of the structure can be extracted using a rectangular or even polygonal selection tool. The so-imported model is ready for simulation, as the right boundary and mesh setting will be automatically selected during the import.
For the presentation of the results, one signal trace named DAT 02 was selected. Adjacent to this signal line, lie the clock N line and the DAT 06 line, as depicted by Fig. 3. The examined line was excited using a Gaussian pulse containing frequency components up to 8 GHz. The time signals plotted in Fig. 4 depict the time development of the input and output pulse, as well as the near and far end crosstalk to the adjacent lines. As the calculation is performed in the time domain, the S-Parameters for the entire frequency range can be obtained from a single simulation, as depicted by Fig. 5. Furthermore, arbitrary time signals can be used for the simulation. However, it is more efficient to extract network parameters from the 3D simulation based on model order reduction, and use the extracted values for a circuit level simulation in CST DESIGN STUDIO™ (CST DS).
The left hand side of Fig. 6 illustrates the schematics of the chip model as displayed by CST DS. In this circuit level simulation, the structure was excited using a rectangular pulse with a rise time of 39.5 ps. The same pulse shape was used by IBM for the measurement of the signal delay time. The value estimated in CST DS amounts to 118.4 ps, showing excellent agreement with the measured value of 118.6 ps.